Design of Programmable, Efficient Finite Impulse Response Filter Based on Distributive Arithmetic Algorithm

Present era of the mobile computing and multimedia technology demands high performance and low power Very Large Scale Integrated Circuit (VLSI) digital signal processing (DSP) systems. The availability of larger Field Programmable Gate Array (FPGA) devices has started a shift of System-on-Chip (SoC) designs towards using reprogrammable FPGAs, thereby starting a new era of System-on-a-reprogrammable-Chip (SoRC). One of the most widely used operations in DSP is Finite Impulse Response (FIR) filtering which performs the weighted summations of input sequences. Due to high speed requirements and increasing complexity of DSP systems, filtering operations have become computationally intensive and power expensive. This makes low power design an important area of research in field of digital design. The design of efficient FIR Filter in terms of low power, less area and high speed is the key issue in all signals processing application. Two designs are discussed in this thesis, one of them is Conventional Unfolded Direct Form FIR Filter core and the other one is the Conventional Unfolded Direct Form FIR Filter Core with distributed arithmetic algorithm. These two designs are compared with each other. In Distributed Arithmetic (DA) the task of summing product terms is replaced by table look-up procedures that are easy to implement in the Xilinx configurable logic block (CLB) look-up table architecture. Distributed Arithmetic (DA) plays a key role in embedding DSP functions in the Xilinx 4000 family of FPGA devices. The results show that the implementation of FIR Filter using DA Algorithm is more efficient as compared to FIR Filter Using Conventional Arithmetic Algorithm.